In recent years, with high integration of a semiconductor device, a multilayer wiring structure is applied. In the multilayer wiring structure, flattening a surface of an interlayer insulating film is required. This is to prevent exposure displacement and the like in forming a wiring to be formed on the interlayer insulating film. As techniques to obtain a flat interlayer insulating film, the following techniques are applied.
(1) A technique in which an insulating film is formed by using ozone-boron phosphorus silicate glass (O3-BPSG), and thereafter, a reflow is performed thereby flattening the surface of the insulating film
(2) A technique in which an insulating film is formed by a chemical vapor deposition method (a CVD method) under reduced pressure, and thereafter, etching back is performed thereby flattening the surface of the insulating film
(3) A technique in which a first insulating film is formed by a CVD method under reduced pressure, and thereafter, a second insulating film is formed on the first insulating film by using SOG (Spin On Glass)
(4) A technique in which an insulating film is formed by a plasma CVD method using TEOS (tetraethylorthosilicate), and thereafter, a CMP (Chemical Mechanical Polishing) is performed thereby flattening the surface of the insulating film
(5) A technique in which an insulating film is formed by a high density plasma CVD method, and thereafter, a CMP is performed thereby flattening the surface of the insulating film
Here, the technique (3) will be explained. FIG. 9A to FIG. 9G are cross-sectional views showing a conventional manufacturing method of a semiconductor device in order of steps.
First, as illustrated in FIG. 9A, an element isolation insulating film 102 is formed on a surface of a semiconductor substrate 101 composed of silicon or the like. Next, an ion implantation of B (boron) is performed in the surface of an element region demarcated by the element isolation insulating film 102 thereby forming a P-well 103. Next, gate insulating films 104 and gate electrodes 105 are formed on the P-well 103. Thereafter, an ion implantation of P (phosphorus) is performed in the surface of the P-well 103 thereby forming shallow impurity diffusion layers 106. Subsequently, sidewall insulating films 107 are formed on lateral sides of the gate electrodes 105. Next, an ion implantation of As (arsenic) is performed in the surface of the P-well 103 thereby forming deep impurity diffusion layers 108. Thus, transistors Tr are formed. Note that the single transistor Tr includes the two impurity diffusion layers 108, and one of them is shared with another transistor Tr. The impurity diffusion layer 108 that is shared constitutes a drain, and the impurity diffusion layer 108 that is not shared constitutes a source.
Next, as illustrated in FIG. 9B, a silicon oxynitride film 111 covering the transistors Tr is formed, and an SOG film 112 is formed thereon. In forming the SOG film 112, a coating solution of SOG is applied on the silicon oxynitride film 111, and thereafter the coating solution of SOG is cured.
Thereafter, as illustrated in FIG. 9C, a resist pattern 191 having openings at positions matching the impurity diffusion layers 108 is formed on the SOG film 112. Then, etching of the SOG film 112 and the silicon oxynitride film 111 is performed by using the resist pattern 191 as a mask thereby forming contact holes 115s reaching the sources and a contact hole 115d reaching the drain.
Subsequently, as illustrated in FIG. 9D, the resist pattern 191 is removed. Next, a barrier metal film (not-illustrated) is formed on the entire surface, and a tungsten film (not-illustrated) is formed thereon. Then, the tungsten film and the barrier metal film are polished until the SOG film 112 is exposed. As a result, contact plugs 116s are formed in the contact holes 115s, and a contact plug 116d is formed in the contact hole 115d. 
Next, as illustrated in FIG. 9E, wirings 117 in contact with the contact plugs 116s and 116d are formed. Thereafter, a silicon oxynitride film 118 covering the wirings 117 is formed, and an SOG film 122 is formed thereon. In forming the SOG film 122, a coating solution of SOG is applied on the silicon oxynitride film 118, and thereafter the coating solution of SOG is cured. Subsequently, an NSG film 125 is formed on the SOG film 122 by a plasma CVD method using TEOS or the like.
Next, as illustrated in FIG. 9F, a resist pattern 192 having openings at positions matching the wirings 117 is formed on the NSG film 125. Then, etching of the NSG film 125 and so on is performed by using the resist pattern 192 as a mask thereby forming contact holes 126 reaching the wirings 117.
Next, as illustrated in FIG. 9G, the resist pattern 192 is removed. Next, a barrier metal film (not-illustrated) is formed on the entire surface, and a tungsten film (not-illustrated) is formed thereon. Then, the tungsten film and the barrier metal film are polished until the NSG film 125 is exposed. As a result, contact plugs 127 are formed in the contact holes 126. Thereafter, upper layer wirings and so on are formed.
However, in the conventional techniques of (1) and (2), embedding by the insulating film is not sufficient in a region where an interval of a level difference due to the gate electrode, the wiring, or the like is wide.
In the conventional technique of (3), as illustrated in FIG. 10A, there is sometimes a case when a void 151 is caused between the SOG film 112 and the silicon oxynitride film 111 in a region where an interval between the gate electrodes 105 is narrow. Then, as illustrated in FIG. 10B, there is sometimes a case when the void 151 and the contact hole 115d get connected. In this case, degas and the like from the silicon oxynitride film 111 are likely to be gathered into the void 151 after the contact plug 116d is formed. Therefore, as illustrated in FIG. 10C, thereafter, deformation or the like of the contact plug 116d is caused, and there is sometimes a case when contact resistance rises.
Further, in the conventional technique of (3), as illustrated in FIG. 11A, in a region where an interval between the wirings 117 is narrow, there is sometimes a case when a void 152 is caused between the SOG film 122 and the silicon oxynitride film 118. Then, as illustrated in FIG. 11B, based on the void 152, there is sometimes a case when a crack 153 is caused in the SOG film 122, the NSG film 125, and the like. Further, as illustrated in FIG. 11C, there is sometimes a case when the void 152 is propagated to the contact hole 126. In this case as well, problems such as a rise of contact resistance are caused.
These voids 151 and 152 are likely to be caused in a portion close to an edge of the semiconductor substrate 101 having a disk shape. The voids 151 and 152 are sometimes called whiskers.
In the conventional technique of (4) as well, similarly to the conventional technique of (3), there is sometimes a case when a void is caused. Further, a time taken for forming the insulating film is long. Further, due to a CMP, the number of steps and cost are increased, and throughput drops.
In the conventional technique of (5) as well, a time taken for forming the insulating film is long. Further, due to a CMP, the number of steps and cost are increased, and throughput drops.
Note that, with respect to the conventional technique of (3), there exists a technique in which the silicon oxynitride film 118 is changed to an NSG film or the like, but the same problem is caused. Further, in place of forming the SOG film 112, there exists a technique in which the conventional technique of (4) is applied to form an insulating film, but a problem in the conventional technique of (4) remains.    Patent Document 1: Japanese Laid-open Patent Publication No. 2005-340266    Patent Document 2: Japanese Laid-open Patent Publication No. 7-153759    Patent Document 3: Japanese Laid-open Patent Publication No. 63-281432    Patent Document 4: Japanese Patent No. 3158288